Hello , in this blog we will verify simple ROM(Read Only Memory) using UVM(Universal Verification Methodology). Here Design ROM is not Programmable i.e, it is hard coded.
Design Description : Reading from ROM is synchronous with clock(clk) , reset is asynchronous.
Address(addr) line is of 5 bits means there are 32 locations in ROM.output(out) vector is of 8bits.
Inputs : addr , clk , rst , rd //only addr is of 5 bits other are single bits
Outputs: out // output vector is 8bits
Test Bench Architecture
In our Test Bench we have main component scoreboard and coverage collector, to see see coverage report download code from edaplayground(link is given at the end) and open coverage_data.html
file.
file.
In scoreboard since addr is of only 5 bits , array is created with same index and value of design for
large design this technique is not reliable.
Design
module ROM(rd,
addr,
out,
clk,
rst
);
parameter ADDR=5; // 32 locations
parameter WIDTH=8;
input rd;
input clk;
input rst;
input [ADDR-1:0]addr;
output reg [WIDTH-1:0]out;
reg [WIDTH-1:0] temp;
always@(posedge clk or posedge rst)
if(rst==1)
begin
out<=0;
end
else
begin
out<=temp;
end
always@(addr or rd)
begin
if(rd)
begin
case(addr)
0:temp=8'h45;
1:temp=8'h60;
2:temp=8'h23;
3:temp=8'h79;
4:temp=8'h12;
5:temp=8'hab;
6:temp=8'hcf;
7:temp=8'h9a;
8:temp=8'hb2;
9:temp=8'hc4;
10:temp=8'h8d;
11:temp=8'h1d;
12:temp=8'h34;
13:temp=8'he4;
14:temp=8'ha6;
15:temp=8'h9d;
16:temp=8'h87;
17:temp=8'h21;
18:temp=8'h3a;
19:temp=8'h0a;
20:temp=8'ha0;
21:temp=8'hbc;
22:temp=8'hcd;
23:temp=8'h67;
24:temp=8'h39;
25:temp=8'hda;
26:temp=8'hd4;
27:temp=8'h9b;
28:temp=8'h5b;
29:temp=8'h6a;
30:temp=8'h7c;
31:temp=8'hc3;
default:temp=8'bx;
endcase
end //end if
else
begin
temp=8'bx;
end
end
endmodule
rom_sequence_item
class rom_sequence_item extends uvm_sequence_item;
//------------ i/p || o/p field declaration-----------------
parameter ADDR=5; // 32 locations
parameter WIDTH=8;
rand logic [ADDR-1:0]addr; //i/p
rand logic rd;
logic [WIDTH-1:0]out; //o/p
logic rst;
//---------------- register rom_sequence_item class with factory --------
`uvm_object_utils_begin(rom_sequence_item)
`uvm_field_int( addr ,UVM_ALL_ON)
`uvm_field_int( rd ,UVM_ALL_ON)
`uvm_field_int( out ,UVM_ALL_ON)
`uvm_field_int( rst ,UVM_ALL_ON)
`uvm_object_utils_end
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
function new(string name="rom_sequence_item");
super.new(name);
endfunction
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// write DUT inputs here for printing
function string input2string();
return($sformatf("addr=%d rd=%0b rst=%0b", addr,rd,rst));
endfunction
// write DUT outputs here for printing
function string output2string();
return($sformatf("out=%8h ", out));
endfunction
function string convert2string();
return($sformatf({input2string(), " ", output2string()}));
endfunction
//----------------------------------------------------------------------------
endclass:rom_sequence_item
rom_sequence
/***************************************************
** class name : rom_sequence
** description : read randomly from rom,
addr is random and rd==1
***************************************************/
class rom_sequence extends uvm_sequence#(rom_sequence_item);
//----------------------------------------------------------------------------
`uvm_object_utils(rom_sequence)
//----------------------------------------------------------------------------
rom_sequence_item txn;
int unsigned loop_count=40;
//----------------------------------------------------------------------------
function new(string name="rom_sequence");
super.new(name);
endfunction
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
virtual task body();
for(int i=0;i<loop_count;i++)
begin
txn=rom_sequence_item::type_id::create("txn");
start_item(txn);
assert(txn.randomize()with{txn.rd==1;});
txn.rst=0;
finish_item(txn);
end
endtask:body
//----------------------------------------------------------------------------
endclass:rom_sequence
/***************************************************
** class name : read_in_order
** description : read from ROM from location 0 to 31
one by one, starting with addr=0
to addr=31 , rd==1
***************************************************/
class read_in_order extends rom_sequence;
//----------------------------------------------------------------------------
`uvm_object_utils(read_in_order)
//----------------------------------------------------------------------------
rom_sequence_item txn;
int unsigned loop_count=32;
//----------------------------------------------------------------------------
function new(string name="read_in_order");
super.new(name);
endfunction
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
task body();
repeat(2)
begin
for(int i=0;i<loop_count;i++)
begin
txn=rom_sequence_item::type_id::create("txn");
start_item(txn);
assert(txn.randomize()with{txn.addr==i; txn.rd==1;});
txn.rst=0;
finish_item(txn);
end
end
endtask:body
//----------------------------------------------------------------------------
endclass
/***************************************************
** class name : read_can_be_zero
** description : here rd signal may or may not be 1,
it can be 1 or 0, address is random
***************************************************/
class read_can_be_zero extends rom_sequence;
//----------------------------------------------------------------------------
`uvm_object_utils(read_can_be_zero)
//----------------------------------------------------------------------------
rom_sequence_item txn;
int unsigned loop_count=32;
//----------------------------------------------------------------------------
function new(string name="read_can_be_zero");
super.new(name);
endfunction
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
task body();
for(int i=0;i<loop_count;i++)
begin
txn=rom_sequence_item::type_id::create("txn");
start_item(txn);
txn.randomize();
txn.rst=0;
finish_item(txn);
end
endtask:body
//----------------------------------------------------------------------------
endclass
class reset extends rom_sequence;
//----------------------------------------------------------------------------
`uvm_object_utils(reset)
//----------------------------------------------------------------------------
rom_sequence_item txn;
//----------------------------------------------------------------------------
function new(string name="reset");
super.new(name);
endfunction
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
task body();
txn=rom_sequence_item::type_id::create("txn");
start_item(txn);
txn.rst=1;
txn.addr=0;
txn.rd=0;
finish_item(txn);
endtask:body
//----------------------------------------------------------------------------
endclass
rom_sequencer
class rom_sequencer extends uvm_sequencer#(rom_sequence_item);
//----------------------------------------------------------------------------
`uvm_component_utils(rom_sequencer)
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
function new(string name="rom_sequencer",uvm_component parent);
super.new(name,parent);
endfunction
//----------------------------------------------------------------------------
endclass:rom_sequencer
rom_driver
class rom_driver extends uvm_driver #(rom_sequence_item);
//----------------------------------------------------------------------------
`uvm_component_utils(rom_driver)
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
function new(string name="",uvm_component parent);
super.new(name,parent);
endfunction
//----------------------------------------------------------------------------
uvm_analysis_port #(rom_sequence_item) drv2sb;
//-------------------------- virtual interface handel -----------------------
virtual interface intf vif;
//----------------------------------------------------------------------------
//------------------------- get interface handel from top -------------------
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!(uvm_config_db#(virtual intf)::get(this,"","vif",vif))) begin
`uvm_fatal("driver","unable to get interface");
end
drv2sb=new("drv2sb",this);
endfunction
//----------------------------------------------------------------------------
//---------------------------- run task --------------------------------------
task run_phase(uvm_phase phase);
rom_sequence_item txn;
forever begin
seq_item_port.get_next_item(txn);
@(posedge vif.clk);
vif.rst = txn.rst;
vif.addr = txn.addr;
vif.rd = txn.rd;
drv2sb.write(txn);
seq_item_port.item_done();
end
endtask
//----------------------------------------------------------------------------
endclass:rom_driver
interface
interface intf(input bit clk);
parameter ADDR=5; // 32 locations
parameter WIDTH=8;
// ------------------- port declaration-------------------------------------
logic [ADDR-1:0]addr;
logic rd;
logic [WIDTH-1:0]out;
logic rst;
//--------------------------------------------------------------------------
endinterface
rom_monitor
class rom_monitor extends uvm_monitor;
//----------------------------------------------------------------------------
`uvm_component_utils(rom_monitor)
//----------------------------------------------------------------------------
//------------------- constructor --------------------------------------------
function new(string name="",uvm_component parent);
super.new(name,parent);
endfunction
//----------------------------------------------------------------------------
//---------------- sequence_item class ---------------------------------------
rom_sequence_item txn;
//----------------------------------------------------------------------------
//------------------------ virtual interface handle---------------------------
virtual interface intf vif;
//----------------------------------------------------------------------------
//------------------------ analysis port -------------------------------------
uvm_analysis_port#(rom_sequence_item) ap_mon;
//----------------------------------------------------------------------------
//------------------- build phase --------------------------------------------
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!(uvm_config_db#(virtual intf)::get(this,"","vif",vif)))
begin
`uvm_fatal("monitor","unable to get interface")
end
ap_mon=new("ap_mon",this);
txn=rom_sequence_item::type_id::create("txn",this);
endfunction
//----------------------------------------------------------------------------
//-------------------- run phase ---------------------------------------------
task run_phase(uvm_phase phase);
forever
begin
@(negedge vif.clk);
txn.rst = vif.rst;
txn.addr = vif.addr;
txn.rd = vif.rd;
txn.out = vif.out;
ap_mon.write(txn);
end
endtask
//----------------------------------------------------------------------------
endclass:rom_monitor
rom_agent
class rom_agent extends uvm_agent;
//----------------------------------------------------------------------------
`uvm_component_utils(rom_agent)
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
function new(string name="",uvm_component parent);
super.new(name,parent);
endfunction
//----------------------------------------------------------------------------
//----------------- class handles --------------------------------------------
rom_sequencer sequencer_h;
rom_driver driver_h;
rom_monitor monitor_h;
//----------------------------------------------------------------------------
//---------------------- build phase -----------------------------------------
function void build_phase(uvm_phase phase);
super.build_phase(phase);
driver_h = rom_driver::type_id::create("driver_h",this);
sequencer_h = rom_sequencer::type_id::create("sequencer_h",this);
monitor_h = rom_monitor::type_id::create("monitor_h",this);
endfunction
//----------------------------------------------------------------------------
//----------------------- connect phase --------------------------------------
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
driver_h.seq_item_port.connect(sequencer_h.seq_item_export);
endfunction
//----------------------------------------------------------------------------
endclass:rom_agent
rom_coverage
class rom_coverage extends uvm_subscriber #(rom_sequence_item);
//----------------------------------------------------------------------------
`uvm_component_utils(rom_coverage)
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
function new(string name="",uvm_component parent);
super.new(name,parent);
dut_cov=new();
endfunction
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
rom_sequence_item txn;
real cov;
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
covergroup dut_cov;
option.per_instance=1;
ADDR :coverpoint txn.addr;
RD :coverpoint txn.rd;
ADDRXRD:cross ADDR,RD;
endgroup:dut_cov
//----------------------------------------------------------------------------
//--------------------- write method ----------------------------------------
function void write(rom_sequence_item t);
txn=t;
dut_cov.sample();
endfunction
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
function void extract_phase(uvm_phase phase);
super.extract_phase(phase);
cov=dut_cov.get_coverage();
endfunction
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
function void report_phase(uvm_phase phase);
super.report_phase(phase);
`uvm_info(get_type_name(),$sformatf("Coverage is %f",cov),UVM_LOW)
endfunction
//----------------------------------------------------------------------------
endclass:rom_coverage
rom_scoreboard
/***************************************************
analysis_port from driver
analysis_port from monitor
***************************************************/
`uvm_analysis_imp_decl( _drv )
`uvm_analysis_imp_decl( _mon )
class rom_scoreboard extends uvm_scoreboard;
`uvm_component_utils(rom_scoreboard)
uvm_analysis_imp_drv #(rom_sequence_item, rom_scoreboard) aport_drv;
uvm_analysis_imp_mon #(rom_sequence_item, rom_scoreboard) aport_mon;
uvm_tlm_fifo #(rom_sequence_item) expfifo;
uvm_tlm_fifo #(rom_sequence_item) outfifo;
int VECT_CNT, PASS_CNT, ERROR_CNT;
bit[7:0] rom_compare[32];
logic [7:0] queue[$];
int count=0;
reg [7:0] t_out;
reg [4:0] t_addr;
logic t_rd;
logic t_rst;
// more efficient way is to writ function for it.
function new(string name="rom_scoreboard",uvm_component parent);
super.new(name,parent);
rom_compare[0] =8'h45;
rom_compare[1] =8'h60;
rom_compare[2] =8'h23;
rom_compare[3] =8'h79;
rom_compare[4] =8'h12;
rom_compare[5] =8'hab;
rom_compare[6] =8'hcf;
rom_compare[7] =8'h9a;
rom_compare[8] =8'hb2;
rom_compare[9] =8'hc4;
rom_compare[10] =8'h8d;
rom_compare[11] =8'h1d;
rom_compare[12] =8'h34;
rom_compare[13] =8'he4;
rom_compare[14] =8'ha6;
rom_compare[15] =8'h9d;
rom_compare[16] =8'h87;
rom_compare[17] =8'h21;
rom_compare[18] =8'h3a;
rom_compare[19] =8'h0a;
rom_compare[20] =8'ha0;
rom_compare[21] =8'hbc;
rom_compare[22] =8'hcd;
rom_compare[23] =8'h67;
rom_compare[24] =8'h39;
rom_compare[25] =8'hda;
rom_compare[26] =8'hd4;
rom_compare[27] =8'h9b;
rom_compare[28] =8'h5b;
rom_compare[29] =8'h6a;
rom_compare[30] =8'h7c;
rom_compare[31] =8'hc3;
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
aport_drv = new("aport_drv", this);
aport_mon = new("aport_mon", this);
expfifo = new("expfifo",this);
outfifo = new("outfifo",this);
endfunction
function void write_drv(rom_sequence_item tr);
`uvm_info("write_drv STIM", tr.input2string(), UVM_MEDIUM)
t_rd = tr.rd;
t_addr = tr.addr;
t_rst = tr.rst;
if(t_rst==1)
begin
t_out=0;
count=0;
end
else if(t_rd==1)
begin
t_out = rom_compare[t_addr];
queue.push_back(t_out);
end
else if(t_rd==0)
begin
t_out = 8'bx;
queue.push_back(t_out);
end
// tr.out =(count<2)?t_out:(queue.push_front());
if(count<=1) tr.out=0;
else tr.out=queue.pop_front();
count=count+1;
void'(expfifo.try_put(tr));
endfunction
function void write_mon(rom_sequence_item tr);
`uvm_info("write_mon OUT ", tr.convert2string(), UVM_MEDIUM)
void'(outfifo.try_put(tr));
endfunction
task run_phase(uvm_phase phase);
rom_sequence_item exp_tr, out_tr;
forever begin
`uvm_info("scoreboard run task","WAITING for expected output", UVM_DEBUG)
expfifo.get(exp_tr);
`uvm_info("scoreboard run task","WAITING for actual output", UVM_DEBUG)
outfifo.get(out_tr);
if (out_tr.out===exp_tr.out) begin
PASS();
`uvm_info ("PASS ",out_tr.convert2string() , UVM_MEDIUM)
end
else begin
ERROR();
`uvm_info ("ERROR [ACTUAL_OP]",out_tr.convert2string() , UVM_MEDIUM)
`uvm_info ("ERROR [EXPECTED_OP]",exp_tr.convert2string() , UVM_MEDIUM)
`uvm_warning("ERROR",exp_tr.convert2string())
end
end
endtask
function void report_phase(uvm_phase phase);
super.report_phase(phase);
if (VECT_CNT && !ERROR_CNT)
`uvm_info("PASSED",$sformatf(" *** TEST PASSED - %0d vectors ran,
%0d vectors passed***",VECT_CNT, PASS_CNT), UVM_LOW)
else
`uvm_info("FAILED",$sformatf("*** TEST FAILED - %0d vectors ran,
%0d vectors passed,%0d vectors failed ***",VECT_CNT, PASS_CNT,
ERROR_CNT), UVM_LOW)
endfunction
function void PASS();
VECT_CNT++;
PASS_CNT++;
endfunction
function void ERROR();
VECT_CNT++;
ERROR_CNT++;
endfunction
endclass
rom_env
class rom_env extends uvm_env;
//---------------------------------------------------------------------------
`uvm_component_utils(rom_env)
//---------------------------------------------------------------------------
//----------------------------------------------------------------------------
function new(string name="",uvm_component parent);
super.new(name,parent);
endfunction
//----------------------------------------------------------------------------
//-------------------- class handles -----------------------------------------
rom_agent agent_h;
rom_coverage coverage_h;
rom_scoreboard scoreboard_h;
//----------------------------------------------------------------------------
//---------------------- build phase -----------------------------------------
function void build_phase(uvm_phase phase);
super.build_phase(phase);
agent_h = rom_agent::type_id::create("agent_h",this);
coverage_h = rom_coverage::type_id::create("coverage_h",this);
scoreboard_h = rom_scoreboard::type_id::create("scoreboard_h",this);
endfunction
//----------------------------------------------------------------------------
//-------------------------- connect phase -----------------------------------
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
agent_h.monitor_h.ap_mon.connect(coverage_h.analysis_export);
agent_h.monitor_h.ap_mon.connect(scoreboard_h.aport_mon);
agent_h.driver_h.drv2sb.connect(scoreboard_h.aport_drv);
endfunction
//----------------------------------------------------------------------------
endclass:rom_env
rom_test
class rom_test extends uvm_test;
//--------------------------------------------------------------------------
`uvm_component_utils(rom_test)
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
function new(string name="",uvm_component parent);
super.new(name,parent);
endfunction
//--------------------------------------------------------------------------
rom_env env_h;
int file_h;
reset rseq;
reset rseq1;
rom_sequence seq;
read_in_order seq1;
read_in_order seq2;
read_can_be_zero seq3;
read_can_be_zero seq4;
//--------------------------------------------------------------------------
function void build_phase(uvm_phase phase);
super.build_phase(phase);
env_h = rom_env::type_id::create("env_h",this);
rseq = reset::type_id::create("rseq");
rseq1 = reset::type_id::create("rseq1");
seq = rom_sequence::type_id::create("seq");
seq1 = read_in_order::type_id::create("seq1");
seq2 = read_in_order::type_id::create("seq2");
seq3 = read_can_be_zero::type_id::create("seq3");
seq4 = read_can_be_zero::type_id::create("seq4");
endfunction
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
function void end_of_elobartion_phase(uvm_phase phase);
//print(); // PRINT TOPOLOGY
$display("End of eleboration phase in agent");
endfunction
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
function void start_of_simulation_phase(uvm_phase phase);
super.start_of_simulation_phase(phase);
$display("start_of_simulation_phase");
file_h=$fopen("LOG_FILE.log","w");
set_report_default_file_hier(file_h);
set_report_severity_action_hier(UVM_INFO,UVM_DISPLAY+UVM_LOG);
env_h.set_report_verbosity_level_hier(UVM_MEDIUM);
print(); //PRINTS TOPOLOGY
endfunction
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
task run_phase(uvm_phase phase);
phase.raise_objection(this);
rseq.start(env_h.agent_h.sequencer_h);
rseq1.start(env_h.agent_h.sequencer_h);
seq.start(env_h.agent_h.sequencer_h);
seq1.start(env_h.agent_h.sequencer_h);
seq2.start(env_h.agent_h.sequencer_h);
seq3.start(env_h.agent_h.sequencer_h);
seq4.start(env_h.agent_h.sequencer_h);
#10;
phase.drop_objection(this);
endtask
//--------------------------------------------------------------------------
endclass:rom_test
tb_pkg
`ifndef TB_PKG
`define TB_PKG
`include "uvm_macros.svh"
package tb_pkg;
import uvm_pkg::*;
`include "rom_sequence_item.sv" // transaction class
`include "rom_sequence.sv" // sequence class
`include "rom_sequencer.sv" // sequencer class
`include "rom_driver.sv" // driver class
`include "rom_monitor.sv"
`include "rom_agent.sv" // agent class
`include "rom_coverage.sv" // coverage class
`include "rom_scoreboard.sv" // scoreboard class
`include "rom_env.sv" // environment class
`include "rom_test.sv" // test
endpackage
`endif
tb_top
`include "interface.sv"
`include "tb_pkg.sv"
module top;
import uvm_pkg::*;
import tb_pkg::*;
bit clk; // external signal declaration
//----------------------------------------------------------------------------
intf i_intf(clk);
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
ROM DUT(.addr(i_intf.addr),
.rd (i_intf.rd),
.out (i_intf.out),
.clk (i_intf.clk),
.rst(i_intf.rst)
);
//----------------------------------------------------------------------------
initial begin
clk<=0;
end
always #5 clk=~clk;
//----------------------------------------------------------------------------
initial begin
$dumpfile("dumpfile.vcd");
$dumpvars;
end
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
initial begin
uvm_config_db#(virtual intf)::set(uvm_root::get(),"","vif",i_intf);
end
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
initial begin
run_test("rom_test");
end
//----------------------------------------------------------------------------
endmodule
Coverage Result
Link for Code : https://www.edaplayground
Thank you , for reading hava a nice day 😊😊👍.
 using UVM(Universal Verification Methodology). Here Design ROM is not...){kind=link}