By
Vivek Dave
At
December 26, 2020
0
Well in this blog spot we will design Up,Down and Up_Down Counter in Verilog HDL. and also different display functions like $display(),$monitor(),$strobe(),$write() and difference between them.
1) Up counter
module up_counter #(
parameter N=4
)(
rst,clk,out
);
input clk,rst;
output reg [N-1:0] out;
always@(posedge clk or posedge rst)
begin
if(rst==1'b1)
begin
out<=0;
end
else
begin
out<=out+1;
end
end
endmodule
TestBench
module tb;
parameter N_TB=4;
reg clk,rst;
wire [N_TB-1:0] out;
up_counter #(.N(N_TB)) DUT(.*);
initial begin
clk=0;rst=1;
end
always #5 clk=~clk;
initial begin
@(posedge clk) rst=0;
#45;
@(posedge clk) rst=1;
@(posedge clk) rst=0;
#200 $finish;
end
initial begin
$dumpfile("file1.vcd");
$dumpvars(1,tb);
$monitor("out = %b",out);
end
endmodule
Link For Code : https://www.edaplayground.com/x/ex3M
2) Down Counter
module down_counter #(
parameter N=4
)(
rst,clk,out
);
input clk,rst;
output reg [N-1:0] out;
always@(posedge clk or posedge rst)
begin
if(rst==1'b1)
begin
out<={{(N-1){1'b1}},1'b1};
end
else
begin
out<=out-1;
end
end
endmodule
TestBench
module tb;
parameter N_TB=8;
reg clk,rst;
wire [N_TB-1:0] out;
down_counter #(.N(N_TB)) DUT(.*);
initial begin
clk=0;rst=1;
end
always #5 clk=~clk;
initial begin
@(posedge clk) rst=0;
#45;
@(posedge clk) rst=1;
@(posedge clk) rst=0;
#200 $finish;
end
initial begin
$dumpfile("file1.vcd");
$dumpvars(1,tb);
$monitor("out = %b",out);
end
endmodule
Link For Down Counter : https://www.edaplayground.com/x/766a
3) Up_Down Counter
module up_down_counter #(
parameter N=4
)(
clk,rst,up_down,out
);
input clk,rst,up_down; //if up_down==1 up counter
output reg [N-1:0]out; // otherwise down counter
always@(posedge clk or posedge rst)
begin
if(rst==1)
begin
out<=0;
end
else
begin
if(up_down==1'b1)
begin
out<=out+1;
end
else
begin
out<=out-1;
end
end
end
endmodule
TestBench
module tb;
parameter N_TB=4;
reg clk,rst,up_down;
wire [N_TB-1:0] out;
up_down_counter #(.N(N_TB)) DUT(.*);
initial begin
clk=0;rst=1;up_down=1;
end
always #5 clk=~clk;
initial begin
@(posedge clk) rst=0;
#45;
@(posedge clk) rst=1;
@(posedge clk) rst=0;
#50 up_down=0;
#60 up_down=1;
#200 $finish;
end
initial begin
$dumpfile("file1.vcd");
$dumpvars(1,tb);
$monitor("out = %b",out);
end
endmodule
Link For Up Down Counter : https://www.edaplayground.com/x/nBU8
Display Tasks
In System Verilog we have 4 display tasks which is $display,$write,$monitor,$strobe. $display and $write executes in active region while $strobe and $monitor executes in postponed region.
$display("string",variables); - executes when encountered
$write("string",variables); - similar to $display but it will not append new line at end i.e \n
$monitor("string",variables); - executes whenever variable changes which is describe inside $monitor
$strobe("string",variables); - similar to $display but executes in postponed region.
module tb;
int a;
initial begin
a=0;
a<=5;
$display("[$display] 1st a=%0d",a);
$strobe("[$strobe] 4rd a=%0d",a);
$monitor("[$monitor] 3th a=%0d",a);
$write("[$write] 2nd a=%0d",a);
end
endmodule
Result
[$display] 1st a=0
[$write] 2nd a=0[$monitor] 3th a=5
[$strobe] 4rd a=5
V C S S i m u l a t i o n R e p o r t
Thank you for reading , have a nice day.😊😊
You Might Also Like
