Hello again, in this blog spot we will design D,T,SR,JK Flip Flops. In all design reset is asynchronous and clock is positive edge trigger.
1) D Fkip Flop
In D flip flop Qn+1=Qn. means Q=D and in reset Q=0.
2) T Flip Flop
In T flip flop if T=1 then Q=~Q and if T=0 then Q=Q. in case of reset Q=0.
TestBench
Waveform
3) SR Flip Flop
TestBench
Waveform
4) JK Flip Flop
TestBench
Waveform
Edaplayground links for above design Codes
// d ff -> https://www.edaplayground.com/x/bvNF
// t ff -> https://www.edaplayground.com/x/9TDL
// sr ff -> https://www.edaplayground.com/x/ueWD
// jk ff -> https://www.edaplayground.com/x/SCMJ
